The present invention relates to a three-state complementary MOS integrated circuit and particularly to an improvement for restraining oscillation of the circuit when a slow pulse is applied at the control input.
FIG. 2 shows a three-state complementary MOS integrated circuit in the prior art. In the figure: 1 is an input terminal (IN); 2 is an output terminal (OUT); 3 is a power supply terminal through which a voltage is supplied; 4 is a GND (ground) terminal. The power supply terminal has a positive potential with respect to the ground terminal 4 is a control input .phi. for determining the state of the output; 6 is an inverted control input .phi. which is an inversion of the control input .phi.5; P1, P2, P3, P4 and P6 are P-channel MOS transistor: N1, N2, N3, N4 and N6 are N-channel transistors; The transistors P1 and N1 form an output circuit 10. The transistors P2 to P4, N2 to N4 form a pre-output stage circuit 20 for driving the output circuit.
Now the operation will be described.
When the control input .phi.5 is low and the inverted control input .phi.6 is high, the transistors P3 and N3 are off, the transistors P4 and N4 are on and the output is in the ENABLE State. Accordingly, when the input terminal 1 is low, a low-level signal appears on the output terminal 2. When the input terminal 1 is high, a high-level signal appears on the output terminal 2.
When the control input .phi.5 is high and the inverted control input .phi.6 is low, the transistors P3 and N3 are on and the transistors P4 and N4 are off. Accordingly, the transistors P1 and N1 are off regardless of the state of the input terminal 1, and the output terminal 2 is in the high-impedance state.
FIG. 3 is a timing chart showing the circuit shown in FIG. 2. At the time (I) in FIG. 3, the transistors P2, N4 and N3 are on and the transistors P3, P4 and N2 are off. At the time (II) in FIG. 3, the transistor P3, P4 and N2 are on and the transistors P2, N4 and N3 are off. If the transistors of the pre-output stage circuit that are on at times (I) and (II) are represented by resistors, the equivalent circuits will be as shown in FIG. 4(a) and FIG. 4(b). Thus, a totempole current flows through the pre-output stage circuit at the times (I) and (II).
A three-state complementary MOS integrated circuit in the prior art is configured as described above. The time delay in the potential level transition between the control signal .phi. and the inverted control input .phi. and at the times when the two signals have the same level, a totempole current flows through the pre-outputs stage circuit. As a result, the gate inputs to the output circuit are unstable. A large totempole current flow through the output circuit and causes fluctuation at the GND terminal, thereby causing oscillation of the device.